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a adsp-21065l information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. rev. c dsp microcomputer summary high performance signal computer for communica- tions, audio, automotive, instrumentation and industrial applications super harvard architecture computer (sharc ) four independent buses for dual data, instruction, and i/o fetch on a single cycle 32-bit fixed-point arithmetic; 32-bit and 40-bit floating- point arithmetic 544 kbits on-chip sram memory and integrated i/o peripheral i 2 s support, for eight simultaneous receive and trans- mit channels key features 66 mips, 198 mflops peak, 132 mflops sustained performance user-configurable 544 kbits on-chip sram memory two external port, dma channels and eight serial port, dma channels sdram controller for glueless interface to low cost external memory (@ 66 mhz) 64m words external address range 12 programmable i/o pins and two timers with event capture options code-compatible with adsp-2106x family 208-lead mqfp or 196-ball mini-bga package 3.3 volt operation flexible data formats and 40-bit extended precision 32-bit single-precision and 40-bit extended-precision ieee floating-point data formats 32-bit fixed-point data format, integer and fractional, with dual 80-bit accumulators parallel computations single-cycle multiply and alu operations in parallel with dual memory read/writes and instruction fetch multiply with add and subtract for accelerated fft but- terfly computation 1024-point complex fft benchmark: 0.274 ms (18,221 cycles) sport 1 4 iop registers (memory mapped) control, status, timer & data buffers i/o processor instruction cache 32 48 bit data addr two independent dual-ported blocks processor port i/o port block 0 block 1 jtag test & emulation 7 host port addr bus mux ioa 17 iod 48 multiprocessor interface dual-ported sram external port data bus mux 32 24 24 pm address bus dm address bus pm data bus dm data bus bus connect (px) data register file 16 40 bit barrel shifter alu multiplier 32 48 40 core processor dma controller program sequencer dag2 8 4 24 sdram interface (i 2 s) (2 rx, 2tx) (2 rx, 2tx) (i 2 s) sport 0 dag1 8 4 32 data data data addr addr addr figure 1. functional block diagram sharc is a registered trademark of analog devices, inc.
rev. c adsp-21065l ? 544 kbits configurable on-chip sram dual-ported for independent access by core processor and dma configurable in combinations of 16-, 32-, 48-bit data and program words in block 0 and block 1 dma controller ten dma channels?wo dedicated to the external port and eight dedicated to the serial ports background dma transfers at up to 66 mhz, in parallel with full speed processor execution performs transfers between: internal ram and host internal ram and serial ports internal ram and master or slave sharc internal ram and external memory or i/o devices external memory and external devices host processor interface efficient interface to 8-, 16-, and 32-bit microprocessors host can directly read/write adsp-21065l iop registers multiprocessing distributed on-chip bus arbitration for glueless, parallel bus connect between two adsp-21065ls plus host 132 mbytes/s transfer rate over parallel bus serial ports independent transmit and receive functions programmable 3-bit to 32-bit serial word width i 2 s support allowing eight transmit and eight receive channels glueless interface to industry standard codecs tdm multichannel mode with -law/a-law hardware companding multichannel signaling protocol
rev. c adsp-21065l ? general description the adsp-21065l is a powerful member of the s harc family of 32-bit processors optimized for cost sensitive appli- cations. the s harc?uper harvard architecture?ffers the highest levels of performance and memory integration of any 32-bit dsp in the industry?hey are also the only dsp in the industry that offer both fixed and floating-point capabilities, without compromising precision or performance. the adsp-21065l is fabricated in a high speed, low power cmos process, 0.35 m m technology. with its on-chip instruc- tion cache, the processor can execute every instruction in a single cycle. table i lists the performance benchmarks for the adsp-21065l. the adsp-21065l sharc combines a floating-point dsp core with integrated, on-chip system features, including a 544 kbit sram memory, host processor interface, dma con- troller, sdram controller, and enhanced serial ports. figure 1 shows a block diagram of the adsp-21065l, illustrat- ing the following architectural features: computation units (alu, multiplier, and shifter) with a shared data register file data address generators (dag1, dag2) program sequencer with instruction cache timers with event capture modes on-chip, dual-ported sram external port for interfacing to off-chip memory and peripherals host port and sdram interface dma controller enhanced serial ports jtag test access port table i. performance benchmarks benchmark timing cycles cycle time 15.00 ns 1 1024-pt. complex fft (radix 4, with digit reverse) 0.274 ns 18221 matrix multiply (pipelined) [3 3] [3 1] 135 ns 9 [4 4] [4 1] 240 ns 16 fir filter (per tap) 15 ns 1 iir filter (per biquad) 60 ns 4 divide y/x 90 ns 6 inverse square root (1/ x ) 135 ns 9 dma transfers 264 mbytes/sec. adsp-21000 family core architecture the adsp-21065l is code and function compatible with the adsp-21060/adsp-21061/adsp-21062. the adsp-21065l includes the following architectural features of the sharc family core. reset adsp-21065l #1 bms addr 23-0 data 31-0 control address data cs addr data boot eprom (optional) addr sdram (optional) data addr data host processor (optional) clock cs hbr hbg redy rd wr ack sbts sw br 2 clkin ms 3-0 cpa cs reset id 1-0 01 tx0_a tx0_b rx0_a rx0_b sport0 tx1_a tx1_b rx1_a rx1_b sport1 cs ras cas dqm sdclk 1-0 sdcke sda10 br 1 ras cas dqm clk cke a10 control sdwe we figure 2. adsp-21065l single-processor system independent, parallel computation units the arithmetic/logic unit (alu), multiplier, and shifter all perform single-cycle instructions. the three units are arranged in parallel, maximizing computational throughput. single multi- function instructions execute parallel alu and multiplier operations. these computation units support ieee 32-bit single- precision floating-point, extended precision 40-bit floating- point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. this 10-port, 32-register (16 primary, 16 secondary) register file, combined with the adsp-21000 harvard architecture, allows unconstrained data flow between computation units and internal memory. single-cycle fetch of instruction and two operands the adsp-21065l features an enhanced super harvard archi- tecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 1). with its separate program and data memory buses, and on-chip instruction cache, the processor can simulta- neously fetch two operands and an instruction (from the cache), all in a single cycle. instruction cache the adsp-21065l includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and two data values. the cache is selective?nly the instructions that fetches conflict with pm bus data accesses are cached. this allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and fft butterfly processing. data address generators with hardware circular buffers the adsp-21065l? two data address generators (dags) implement circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data
rev. c adsp-21065l ? struc tures required in digital signal processing, and are com- monly used in digital filters and fourier transforms. the adsp- 21065l? two dags contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wraparound, reducing overhead, increasing perfor- mance, and simplifying implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp- 21065l can conditionally execute a multiply, an add, a subtract and a branch, all in a single instruction. adsp-21065l features the adsp-21065l is designed to achieve the highest system throughput to enable maximum system performance. it can be clocked by either a crystal or a ttl-compatible clock signal. the adsp-21065l uses an input clock with a frequency equal to half the instruction rate? 33 mhz input clock yields a 15 ns processor cycle (which is equivalent to 66 mhz). inter- faces on the adsp-21065l operate as shown below. hereafter in this document, 1x = input clock frequency, and 2x = process or? instruction rate. the following clock operation ratings are based on 1x = 33 mhz (instruction rate/core = 66 mhz): sdram 66 mhz external sram 33 mhz serial ports 33 mhz multiprocessing 33 mhz host (asynchronous) 33 mhz augmenting the adsp-21000 family core, the adsp-21065l adds the following architectural features: dual-ported on-chip memory the adsp-21065l contains 544 kbits of on-chip sram, organized into two banks: bank 0 has 288 kbits, and bank 1 has 256 kbits. bank 0 is configured with 9 columns of 2k 16 bits, and bank 1 is configured with 8 columns of 2k 16 bits. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor or dma controller. the dual-ported memory and separate on-chip buses allow two data transfers from the core and one from i/o, all in a single cycle (see figure 4 for the adsp-21065l memory map). on the adsp-21065l, the memory can be configured as a maximum of 16k words of 32-bit data, 34k words for 16-bit data, 10k words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 544 kbits. all the memory can be accessed as 16-bit, 32-bit or 48-bit. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm and pm busses in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. in this case, the instruction must be available in the cache. single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the adsp-21065l? external port. off-chip memory and peripherals interface the adsp-21065l? external port provides the processor? interface to off-chip memory and peripherals. the 64m words, off-chip address space is included in the adsp-21065l? unified address space. the separate on-chip buses?or program memory, data memory and i/o?re multiplexed at the external port to create an external system bus with a single 24-bit address bus, four memory selects, and a single 32-bit data bus. the on-chip super harvard architecture provides three bus performance, while the off-chip unified address space gives flexibility to the designer. sdram interface the sdram interface enables the adsp-21065l to transfer data to and from synchronous dram (sdram) at 2x clock frequency. the synchronous approach coupled with 2x clock frequency supports data transfer at a high throughput?p to 220 mbytes/sec. the sdram interface provides a glueless interface with stan- dard sdrams?6 mb, 64 mb, and 128 mb?nd includes options to support additional buffers between the adsp-21065l and sdram. the sdram interface is extremely flexible and provides capability for connecting sdrams to any one of the adsp-21065l? four external memory banks. systems with several sdram devices connected in parallel may require buffering to meet overall system timing requirements. the adsp-21065l supports pipelining of the address and control signals to enable such buffering between itself and multiple sdram devices. host processor interface the adsp-21065l? host interface provides easy connection to standard microprocessor buses?-, 16-, and 32-bit?equiring little additional hardware. supporting asynchronous transfers at speeds up to 1x clock frequency, the host interface is accessed through the adsp-21065l? external port. two channels of dma are available for the host interface; code and data trans- fers are accomplished with low software overhead. the host processor requests the adsp-21065l? external bus with the host bus request ( hbr ), host bus grant ( hbg ), and ready (redy) signals. the host can directly read and write the iop registers of the adsp-21065l and can access the dma channel setup and mailbox registers. vector interrupt support enables efficient execution of host commands. dma controller the adsp-21065l? on-chip dma controller allows zero- overhead, nonintrusive data transfers without processor inter- vention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the adsp-21065l? internal memory and either external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp-21065l? internal memory and its serial ports. dma transfers between external memory and external peripheral devices are another option. external bus packing to 16-, 32-, or 48-bit internal words is performed during dma transfers. ten channels of dma are available on the adsp-21065l eight via the serial ports, and two via the processor? external port (for either host processor, other adsp-21065l, memory or
rev. c adsp-21065l ? i/o transfers). programs can be downloaded to the adsp-21065l using dma transfers. asynchronous off-chip peripherals can control two dma channels using dma request/grant lines ( dmar 1-2, dmag 1-2 ). other dma features include interrupt generation on completion of dma transfers and dma chaining for automatically linked dma transfers. serial ports the adsp-21065l features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. the serial ports can operate at 1x clock frequency, providing each with a maximum data rate of 33 mbit/s. each serial port has a primary and a secondary set of transmit and receive channels. independent transmit and receive functions provide greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via dma. each of the serial ports supports three operation modes: dsp serial port mode, i 2 s mode (an interface commonly used by audio codecs), and tdm (time division multiplex) multichannel mode. the serial ports can operate with little-endian or big-endian transmission formats, with selectable word lengths of 3 bits to 32 bits. they offer selectable synchronization and transmit modes and optional m -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. the serial ports also include keyword and keymask features to enhance interprocessor communication. programmable timers and general-purpose i/o ports the adsp-21065l has two independent timer blocks, each of which performs two functions?ulsewidth generation and pulse count and capture. in pulsewidth generation mode, the adsp-21065l can gener- a te a modulated w aveform with an arbitrary pulsewidth within a maximum period of 71.5 secs. in pulse counter mode, the adsp-21065l can measure either the high or low pulsewidth and the period of an input waveform. the adsp-21065l also contains twelve programmable, general purpose i/o pins that can function as either input or output. as output, these pins can signal peripheral devices; as input, these pins can provide the test for conditional branching. program booting the internal memory of the adsp-21065l can be booted at system power-up from an 8-bit eprom, a host processor, or external memory. selection of the boot source is controlled by the bms (boot memory select) and bsel (eprom boot) pins. either 8-, 16-, or 32-bit host processors can be used for booting. for details, see the descriptions of the bms and bsel pins in the pin descriptions section of this data sheet. multiprocessing the adsp-21065l offers powerful features tailored to multi- processing dsp systems. the unified address space allows di rect interprocessor accesses of both adsp-21065l? iop registers. distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing a maximum of two adsp-21065ls and a host processor. master processor changeover incurs only one cycle of overhead. bus lock allows indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 132 mbytes/sec over the external port. development tools the adsp-21065l is supported with a complete set of software and hardware development tools, including the ez-ice in- circuit emulator and development software. the same ez-ice hardware that you use for the adsp-21060/ adsp-21062 also fully emulates the adsp-21065l. both the sharc development tools family and the visualdsp integrated project management and debugging environment support the adsp-21065l. the visualdsp project management environment enables you to develop and debug an application from within a single integrated program. the sharc development tools include an easy to use assem- bler that is based on an algebraic syntax; an assembly library/ librarian; a linker; a loader; a cycle-accurate, instruction-level simulator; a c compiler; and a c run-time library that includes dsp and mathematical functions. debugging both c and assembly programs with the visual dsp debugger, you can: view mixed c and assembly code insert break points set watch points trace bus activity profile program execution fill and dump memory create custom debugger windows the visual ide enables you to define and manage multiuser projects. its dialog boxes and property pages enable you to configure and manage all of the sharc development tools. this capability enables you to: control how the development tools process inputs and gen- erate outputs. maintain a one-to-one correspondence with the tool? com- mand line switches. the ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-21065l processor to monitor and control the target board processor during emulation. the ez-ice provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonintrusive in-circuit emulation is assured by the use of the processor? jtag inter- face?he emulator does not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc pc plug-in cards multiprocessor sharc vme boards, and daughter and modules with multiple sharcs and additional memory. these modules are based on the sharcpac module specification. third party software tools include an ada compiler, dsp libraries, operating systems, and block diagram design tools. additional information for detailed information on the adsp-21065l instruction set and architecture, see the adsp-21065l sharc user? manual , third edition, and the adsp-21065l sharc technical reference. ez-ice and visualdsp are registered trademarks of analog devices, inc. sharcpac is a trademark of analog devices, inc.
rev. c adsp-21065l ? cpa br 2 br 1 control adsp-21065l #2 addr 23-0 data 31-0 reset clkin reset adsp-21065l #1 bms addr 23-0 data 31-0 control address data cs addr data boot eprom (optional) addr sdram (optional) data addr data host processor (optional) clock cs hbr hbg redy rd wr ack sbts sw clkin ms 3-0 cpa cs reset id 1-0 sport0 sport1 cs ras cas dqm sdclk 1-0 sdcke sda10 br 1 ras cas dqm clk cke a10 sdwe we sport0 sport1 control id 1-0 01 10 br 2 figure 3. multiprocessing system
rev. c adsp-21065l ? pin descriptions adsp-21065l pin definitions are listed below. inputs identified as synchronous (s) must meet timing requirements with respect t o clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to vdd or gnd, except for addr 23-0, data 31-0 , flag 11-0 , sw , and inputs that have internal pull-up or pull-down resistors ( cpa , ack, dtxx, drxx, tclkx, rclkx, tms, and tdi)?hese pins can be left float- ing. these pins have a logic-level hold circuit that prevents the input from floating internally. i = input s = synchronous p = power supply (o/d) = open drain o = output a = asynchronous g = ground (a/d) = active drive t = three-state (when sbts is asserted, or when the adsp-2106x is a bus slave) pin type function addr 23-0 i/o/t external bus address . the adsp-21065l outputs addresses for external memory and peripherals on th ese pins. in a multiprocessor system the bus master outputs addresses for read/ writes of the iop registers of the other adsp-21065l. the adsp-21065l inputs addresses when a host processor or multiprocessing bus master is reading or writing its iop registers. data 31-0 i/o/t external bus data . the adsp-21065l inputs and outputs data and instructions on these pins. the external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed- point data over bits 31-0. 16-bit short word data is transferred over bits 15-0 of the bus. pull-up resistors on unused data pins are not necessary. ms 3-0 i/o/t memory select lines . these lines are asserted as chip selects for the corresponding banks of external memory. internal addr 25-24 are decoded into ms 3-0 . the ms 3-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 3-0 lines are inactive; they are active, however, when a condi- tional memory access instruction is executed, whether or not the condition is true. additionally, an ms 3-0 line which is mapped to sdram may be asserted even when no sdram access is active. in a multiprocessor system, the ms 3-0 lines are output by the bus master. rd i/o/t memory read strobe . this pin is asserted when the adsp-21065l reads from external memory devices or from the iop register of another adsp-21065l. external devices (including another adsp-21065l) must assert rd to read from the adsp-21065l? iop registers. in a multipro- cessor system, rd is output by the bus master and is input by another adsp-21065l. wr i/o/t memory write strobe. this pin is asserted when the adsp-21065l writes to external memory devices or to the iop register of another adsp-21065l. external devices must assert wr to write to the adsp-21065l? iop registers. in a multiprocessor system, wr is output by the bus master and is input by the other adsp-21065l. sw i/o/t synchronous write select. this signal interfaces the adsp-21065l to synchronous memory devices (including another adsp-21065l). the adsp-21065l asserts sw to provide an early indication of an impending write cycle, which can be aborted if wr is not later asserted (e.g., in a conditional write instruction). in a multiprocessor system, sw is output by the bus master and is input by the other adsp-21065l to determine if the multiprocessor access is a read or write. sw is asserted at the same time as the address output. ack i/o/s memory acknowledge . external devices can deassert ack to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. the adsp-21065l deasserts ack as an output to add wait states to a synchronous access of its iop registers. in a multiprocessor system, a slave adsp-21065l deasserts the bus master? ack input to add wait state(s) to an access of its iop registers. the bus master has a keeper latch on its ack pin that maintains the input at the level to which it was last driven. sbts i/s suspend bus three-state. external devices can assert sbts to place the external bus address, data, selects, and strobes?ut not sdram control pins?n a high impedance state for the following cycle. if the adsp-21065l attempts to access external memory while sbts is as- serted, the processor will halt and the memory access will not finish until sbts is deasserted. sbts should only be used to recover from host processor/adsp-21065l deadlock. irq 2-0 i/a interrupt request lines. may be either edge-triggered or level-sensitive. flag 11-0 i/o/a flag pins. each is configured via control bits as either an input or an output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals.
rev. c adsp-21065l ? pin type function hbr i/a host bus request. must be asserted by a host processor to request control of the adsp- 21065l? external bus. when hbr is asserted in a multiprocessing system, the adsp-21065l that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp- 21065l places the address, data, select, and strobe lines in a high impedance state. it does, however, continue to drive the sdram control pins. hbr has priority over all adsp-21065l bus requests ( br 2-1 ) in a multiprocessor system. hbg i/o host bus grant . acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted by the adsp-21065l until hbr is released. in a multiprocessor system, hbg is output by the adsp-21065l bus master. cs i/a chip select. asserted by host processor to select the adsp-21065l. redy (o/d) o host bus acknowledge. the adsp-21065l deasserts redy to add wait states to an asyn- chronous access of its internal memory or iop registers by a host. open drain output (o/d) by default; can be programmed in adredy bit of syscon register to be active drive (a/d). redy will only be output if the cs and hbr inputs are asserted. dmar 1 i/a dma request 1 (dma channel 9). dmar 2 i/a dma request 2 (dma channel 8). dmag 1 o/t dma grant 1 (dma channel 9). dmag 2 o/t dma grant 2 (dma channel 8). br 2-1 i/o/s multiprocessing bus requests. used by multiprocessing adsp-21065ls to arbitrate for bus mastership. an adsp-21065l drives its own br x line (corresponding to the value of its id 2-0 inputs) only and monitors all others. in a uniprocessor system, tie both br x pins to vdd. id 1-0 i multiprocessing id. determines which multiprocessor bus request ( br 1 br 2 ) is used by adsp-21065l. id = 01 corresponds to br 1 , id = 10 corresponds to br 2 . id = 00 in single- processor systems. these lines are a system configuration selection which should be hard-wired or changed only at reset. cpa (o/d) i/o core priority access. asserting its cpa pin allows the core processor of an adsp-21065l bus slave to interrupt background dma transfers and gain access to the external bus. cpa is an open drain output that is connected to both adsp-21065ls in the system. the cpa pin has an internal 5 k w pull-up resistor. if core access priority is not required in a system, leave the cpa pin unconnected. dtxx o data transmit (serial ports 0, 1; channels a, b). each dtxx pin has a 50 k w internal pull- up resistor. drxx i data receive (serial ports 0, 1; channels a, b). each drxx pin has a 50 k w internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k w internal pull-up resistor. rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k w internal pull-up resistor. tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). bsel i eprom boot select. when bsel is high, the adsp-21065l is configured for booting from an 8-bit eprom. when bsel is low, the bsel and bms inputs determine booting mode. see bms for details. this signal is a system configuration selection which should be hardwired.
rev. c adsp-21065l ? pin type function bms i/o/t * boot memory select. output: used as chip select for boot eprom devices (when bsel = 1). in a multiprocessor system, bms is output by the bus master. input: when low, indicates that no booting will occur and that the adsp-21065l will begin executing instructions from exter- nal memory. see following table. this input is a system configuration selection which should be hardwired. * three-statable only in eprom boot mode (when bms is an output). bsel bms booting mode 1o utput eprom (connect bms to eprom chip select). 01 (input) host processor (hbw [syscon] bit selects host bus width). 00 (input) no booting. processor executes from external memory. clkin i clock in. us ed in conjunction with xtal, configu res the adsp-21065l to use either its internal clock generator or an external clock source. the external crystal should be rated at 1x frequency. connecting the necessary components to clkin and xtal enables the internal clock genera- tor. the adsp-21065l? internal clock generator multiplies the 1x clock to generate 2x clock for its core and sdram. it drives 2x clock out on the sdclkx pins for the sdram interface to use. see also sdclkx. connecting the 1x external clock to clkin while leaving xtal unconnected configures the adsp-21065l to use the external clock source. the instruction cycle rate is equal to 2x clkin. clkin may not be halted, changed, or operated below the specified frequency. reset i/a processor reset. resets the adsp-21065l to a known state and begins execution at the pro gram memory location specified by the hardware reset vector address. this input must be asserted at power-up. tck i test clock (jtag). provides an asynchronous clock for jtag boundary scan. tms i/s test mode select (jtag). used to control the test state machine. tms has a 20 k w internal pull-up resistor. tdi i/s test data input (jtag). provides serial data for the boundary scan logic. tdi has a 20 k w internal pull-up resistor. tdo o test data output (jtag). serial scan output of the boundary scan path. trst i/a test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21065l. trst has a 20 k w internal pull-up resistor. emu (o/d) o emulation status. must be connected to the adsp-21065l ez-ice target board connector only. bmstr o bus master output. in a multiprocessor system, indicates whether the adsp-21065l is cur- rent bus master of the shared external bus. the adsp-21065l drives bmstr high only while it is the bus master. in a single-processor system (id = 00), the processor drives this pin high. cas i/o/t sdram column access strobe. provides the column address. in conjunction with ras , ms x, sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. ras i/o/t sdram row access strobe. provides the row address. in conjunction with cas , ms x, sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. sdwe i/o/t sdram write enable. in conjunction with cas , ras , ms x, sdclkx, and sometimes sda10, defines the operation for the sdram to perform. dqm o/t sdram data mask. in write mode, dqm has a latency of zero and is used to block write operations. sdclk 1-0 i/o/s/t sdram 2x clock output. in systems with multiple sdram devices connected in parallel, supports the corresponding increased clock load requirements, eliminating need of off-chip clock buffers. either sdclk 1 or both sdclkx pins can be three-stated. sdcke i/o/t sdram clock enable. enables and disables the clk signal. for details, see the data sheet supplied with your sdram device.
rev. c adsp-21065l ?0 pin type function sda10 o/t sdram a10 pin. enables applications to refresh an sdram in parallel with a host access. xtal o crystal oscillator terminal. used in conjunction with clkin to enable the adsp-21065l? internal clock generator or to disable it to use an external clock source. see clkin. pwm_event 1-0 i/o/a pwm output/event capture. in pwmout mode, is an output pin and functions as a timer counter. in width_cnt mode, is an input pin and functions as a pulse counter/event capture. vdd p power supply; nominally +3.3 v dc. (33 pins) gnd g power supply return . (37 pins) nc do not connect. reserved pins that must be left open and unconnected. (7 pins) clock signals the adsp-21065l can use an external clock or a crystal. see clkin pin description. you can configure the adsp-21065l to use its internal clock generator by connecting the necessary components to clkin and xtal. you can use either a crystal operating in the fundamental mode or a crystal operating at an overtone. figure 4 shows the component connections used for a c rystal operating in fundamental mode, and figure 5 shows the component connections used for a crystal operating at an overtone. clkin x1 xtal c1 c2 suggested components for 30 mhz operation: ecliptek ec2sm-33-30.000m (surface mount package) ecliptek ec-33-30.000m (through-hole package) c1 = 33pf c2 = 27pf note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. figure 4. 30 mhz operation (fundamental mode crystal) clkin xtal c1 c2 suggested components for 30mhz operation: ecliptek ec2sm-t-30.000m (surface mount package) ecliptek ect-30.000m (through-hole package) c1 = 18pf c2 = 27pf c3 = 75pf l 1 = 3300nh r s = see note. note: c1, c2, c3, r s and l 1 are specific to crystal specified for x1. contact manufacturer for details. c3 r s l1 x1 figure 5. 30 mhz operation (3rd overtone crystal) target board connector for ez-ice probe the adsp-2106x ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-2106x to monitor and con- trol the target board processor during emulation. the ez-ice probe requires the adsp-2106x? clkin, tms, tck, trst , tdi, tdo, emu and gnd signals be made accessible on the target system via a 14-pin connector (a 2 row x 7 pin strip header) such as that shown in figure 6. the ez-ice probe plugs directly onto this connector for chip-on-board emulation. you must add this connector to your target board design if you, intend to use the adsp-2106x ez-ice. the total trace length between the ez-ice connector and the furthest device sharing the ez-ice jtag pins should be lim- ited to 15 inches maximum for guaranteed operation. this restriction on length must include ez-ice jtag signals, which are routed to one or more 2106x devices or to a combination of 2106xs and other jtag devices on the chain. the 14-pin, 2-row pin strip header is keyed at the pin 3 loca- tion?ou must remove pin 3 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spac- ing should be 0.1 0.1 inches. pin strip headers are available from vendors such as 3m, mckenzie and samtec. top view 13 14 11 12 910 9 78 5 6 34 12 emu clkin (optional) tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd figure 6. target board connector for adsp-2106x ez-ice (jtag header)
rev. c adsp-21065l ?1 the btms, btck, btrst and btdi signals are provided so that the test access port can also be used for board-level testing. when the connector is not being used for emulation, place jumpers between the bxxx pins and the xxx pins. if you are not going to use the test access port for board testing, tie btrst to gnd and tie or pull-up btck to v dd . the trst pin must be asserted after power-up (through btrst on the connector) or held low for proper operation of the adsp-2106x. n one of the bxxx pins (pins 5, 7, 9, 11) are connected on the ez-ice probe. the jtag signals are terminated on the ez-ice probe as follows: signal termination tms driven through 22 w resistor (16 ma driver) tck driven at 10 mhz through 22 w resistor (16 ma driver) trst * driven through 22 w resistor (16 ma driver) (pulled up by on-chip 20 k w resistor) tdi driven by 22 w resistor (16 ma driver) tdo one ttl load, split termination (160/220) clkin one ttl load, split termination (160/220). (caution: do not connect to clkin if internal xtal oscillator is used.) emu active low 4.7 k w pull-up resistor, one ttl load (open-drain output from adsp-2106xs) * trst is driven low until the ez-ice probe is turned on by the emulator at software start-up. after software start-up, trst is driven high. connecting clkin to pin 4 of the ez-ice header is optional. the emulator only uses clkin when directed to perform operations such as starting, stopping, and single-stepping two adsp-21065ls in a synchronous manner. if you do not need these operations to occur synchronously on the two processors, simply tie pin 4 of the ez-ice header to ground. for systems which use the internal clock generator and an external discrete crystal, do not directly connect the clkin pin to the jtag probe. this will load the oscillator circuit and possibly cause it to fail to oscillate. instead the jtag probe? clkin can be driven by the xtal pin through a high impedance buffer. if synchronous multiprocessor operations are needed and clkin is connected, clock skew between multiple adsp-2106x processors and the clkin pin on the ez-ice header must be minimal. if the skew is too large, synchronous operations may be off by one cycle between processors. for synchronous multi- processor operation tck, tms, clkin and emu should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. if synchronous multiprocessor operations are not needed (i.e., clkin is not connected), just use appropriate parallel termina- tion on tck and tms. tdi, tdo, emu and trst are not critical signals in terms of skew. for complete information on the sharc ez-ice, see the adsp-21000 family j tag ez-ice user? guide and reference .
rev. c ?2 adsp-21065l?pecifications recommended operating conditions test c grade k grade parameter conditions min max min max unit v dd supply voltage 3.13 3.60 3.13 3.60 v t case case operating temperature ?0 +100 0 +85 c v ih high level input voltage @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 v v il1 low level input voltage 1 @ v dd = min ?.5 0.8 ?.5 0.8 v v il2 low level input voltage 2 @ v dd = min ?.5 0.7 ?.5 0.7 v note see environmental conditions for information on thermal specifications. electrical characteristics c and k grades parameter test conditions min max unit v oh high level output voltage 3 @ v dd = min, i oh = ?.0 ma 4 2.4 v v ol low level output voltage 3 @ v dd = min, i ol = 4.0 ma 4 0.4 v i ih high level input current 5 @ v dd = max, v in = v dd max 10 m a i il low level input current 5 @ v dd = max, v in = 0 v 10 m a i ilp low level input current 6 @ v dd = max, v in = 0 v 150 m a i ozh three-state leakage current 7, 8, 9, 10 @ v dd = max, v in = v dd max 10 m a i ozl three-state leakage current 7 @ v dd = max, v in = 0 v 8 m a i ozls three-state leakage current 8 @ v dd = max, v in = 0 v 150 m a i ozla three-state leakage current 11 @ v dd = max, v in = 1.5 v 350 m a i ozlar three-state leakage current 10 @ v dd = max, v in = 0 v 4 ma i ozlc three-state leakage current 9 @ v dd = max, v in = 0 v 1.5 ma c in input capacitance 12, 13 f in = 1 mhz, t case = 25 c, v in = 2.5 v 8 pf notes 1 applies to input and bidirectional pins: data 31-0 , addr 23-0 , bsel, rd , wr , sw , ack, sbts , irq 2-0 , flag 11-0 , hbg , cs , dmar1 , dmar2 , br 2-1 , id 2-0 , rpba, cpa , tfs0, tfs1, rfs0, rfs1, bms , tms, tdi, tck, hbr , dr0a, dr1a, dr0b, dr1b, tclk0, tclk1, rclk0, rclk1, reset , trst , pwm_event0, pwm_event1, ras , cas , sdwe , sdcke . 2 applies to input pin clkin. 3 applies to output and bidirectional pins: data 31-0 , addr 23-0 , ms 3-0 , rd , wr , sw , ack, flag 11-0 , hbg , redy, dmag1 , dmag2 , br 2-1 , cpa , tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, dt0a, dt1a, dt0b, dt1b, xtal, bms , tdo, emu , bmstr, pwm_event0, pwm_event1, ras , cas , dqm, sdwe , sdclk0, sdclk1, sdcke , sda10. 4 see output drive currents for typical drive current capabilities. 5 applies to input pins: ack, sbts , irq 2-0 , hbr , cs , dmar1 , dmar2 , id 1-0 , bsel, clkin, reset , tck (note that ack is pulled up internally with 2 k w during reset in a multiprocessor system, when id 1-0 = 01 and another adsp-21065l is not requesting bus mastership.) 6 applies to input pins with internal pull-ups: dr0a, dr1a, dr0b, dr1b, trst , tms, tdi. 7 applies to three-statable pins: data 31-0 , addr 23-0 , ms 3-0 , rd , wr , sw , ack, flag 11-0 , redy, hbg , dmag 1 , dmag 2 , bms , tdo, ras , cas , dqm, sdwe , sdclk0, sdclk1, sdcke , sda10, and emu (note that ack is pulled up internally with 2 k w during reset in a multiprocessor system, when id 1-0 = 01 and another adsp-21065l is not requesting bus mastership). 8 applies to three-statable pins with internal pull-ups: dt0a, dt1a, dt0b, dt1b, tclk0, tclk1, rclk0, rclk1. 9 applies to cpa pin. 10 applies to ack pin when pulled up. 11 applies to ack pin when keeper latch enabled. 12 guaranteed but not tested. 13 applies to all signal pins. specifications subject to change without notice. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . . . . ?.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . . ?.5 v to v dd + 0.5 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . . 130 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c lead temperature (5 seconds) . . . . . . . . . . . . . . . . . . . 280 c * stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21065l features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. c adsp-21065l ?3 power dissipation adsp-21065l these specifications apply to the internal power portion of v dd only. see the power dissipation section of this data sheet for calcula- tion of external supply current and total supply current. for a complete discussion of the code used to measure power dissipati on, see the technical note sharc power dissipation measurements. specifications are based on the following operating scenarios: table ii. internal current measurements peak activity high activity operation (i ddinpeak )(i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles to estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state: % peak i ddinpeak + % high i ddinhigh + % low i ddinlow + % idle i ddidle = power consumption (see note 4 below table iii.) or % peak i ddinpeak + % high i ddinhigh + % low i ddinlow + % idle 16 i ddidle 16 = power consumption (see note 5 below table iii.) table iii. internal current measurement scenarios parameter test conditions max unit i ddinpeak supply current (internal) 1 t ck = 33 ns, v dd = max 470 ma t ck = 30 ns, v dd = max 510 ma i ddinhigh supply current (internal) 2 t ck = 33 ns, v dd = max 275 ma t ck = 30 ns, v dd = max 300 ma i ddinlow supply current (internal) 3 t ck = 33 ns, v dd = max 240 ma t ck = 30 ns, v dd = max 260 ma i ddidle supply current (idle) 4 t ck = 33 ns, v dd = max 150 ma t ck = 30 ns, v dd = max 155 ma i ddidle16 supply current (idle16) 5 v dd = max 50 ma notes 1 the test program used to measure i ddinpeak represents worst-case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. 3 i ddinlow is a composite average based on a range of low activity code. 4 idle denotes adsp-21065l state during execution of idle instruction. 5 idle16 denotes adsp-21065l state during execution of idle16 instruction. timing specifications general notes two speed grades of the adsp-21065l are offered, 60 mhz and 66 mhz instruction rates. the specifications shown are based on a clkin frequency of 30 mhz (t ck = 33.3 ns). the dt derating allows specifications at other clkin frequencies (within the min max range of the t ck specification; see cl ock input below). dt is the difference between the actual clkin period and a clkin period of 33.3 ns: dt = ( t ck ?33.3)/32 use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while a ddi- tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statis tical varia- tions and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. see figure 27 in equivalent device loading for ac measurements (includes all fixtures) for voltage reference levels.
rev. c adsp-21065l ?4 switching characteristics specify how the processor changes its signals. you have no control over this timing?ircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the pro cessor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device c on- nected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera- tion. timing requirements guarantee that the processor operates correctly with other devices. (o/d) = open drain (a/d) = active drive 66 mhz 60 mhz parameter min max min max unit clock input timing requirements: t ck clkin period 30.00 100 33.33 100 ns t ckl clkin width low 7.0 7.0 ns t ckh clkin width high 5.0 5.0 ns t ckrf clkin rise/fall (0.4 v?.0 v) 3.0 3.0 ns clkin t ckh t ck t ckl figure 7. clock input parameter min max unit reset timing requirements: t wrst reset pulsewidth low 1 2 t ck ns t srst reset setup before clkin high 2 23.5 + 24 dt t ck ns notes 1 applies after the power-up sequence is complete. at power-up, the processor? internal phase-locked loop requires no more than 3000 clkin cycles while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). 2 only required if multiple adsp-2106xs must come out of reset synchronous to clkin with program counters (pc) equal (i.e., for a simd system). not required for multiple adsp-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synch ronizes itself automatically after reset. clkin reset t wrst t srst figure 8. reset parameter min max unit interrupts timing requirements: t sir irq 2-0 setup before clkin high or low 1 11.0 + 12 dt ns t hir irq 2-0 hold before clkin high or low 1 0.0 + 12 dt ns t ipw irq 2-0 pulsewidth 2 2.0 + t ck /2 ns notes 1 only required for irq x recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met.
rev. c adsp-21065l ?5 clkin irq 2-0 t ipw t sir t hir figure 9. interrupts parameter min max unit timer timing requirements: t sti timer setup before sdclk high 0.0 ns t hti timer hold after sdclk high 6.0 ns switching characteristics: t dtex timer delay after sdclk high 1.0 ns t htex timer hold after sdclk high ?.0 ns parameter min max unit flags timing requirements: t sfi flag 11-0 in setup before sdclk high 1 ?.0 ns t hfi flag 11-0 in hold after sdclk high 1 6.0 ns switching characteristics: t dfo flag 11-0 out delay after sdclk high 1.0 ns t hfo flag 11-0 out hold after sdclk high ?.0 ns t dfoe sdclk high to flag 11-0 out enable ?.0 ns t dfod sdclk high to flag 11-0 out disable ?.75 ns note 1 flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle. sdclk flag 11?0 out flag output t dfo t hfo t dfo t dfod t dfoe sdclk t sfi t hfi flag 11?0 in figure 10. flags
rev. c adsp-21065l ?6 memory read?us master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21065l is the bus master when accessing external memory space. these switching characteristics also apply for bus master synchronous read/write timing (see synchronous read/write?us master below). if these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). an exception to this is the ack pin timing requirements as described in the note below. parameter min max unit timing requirements: t dad address, selects delay to data valid 1, 2 28.0 + 32 dt + w ns t drld rd low to data valid 1 24.0 + 26 dt + w ns t hda data hold from address selects 3 0.0 ns t hdrh data hold from rd h igh 3 0.0 ns t daak ack delay from address, selects 2, 3 24.0 + 30 dt + w ns t dsak ack delay from rd low 3 19.5 + 24 dt + w ns switching characteristics: t drha address, selects hold after rd high ?.0 + h ns t darl address, selects to rd low 2 3.0 + 6 dt ns t rw rd pulsewidth 25.0 + 26 dt + w ns t rwr rd high to wr , rd low 4.5 + 6 dt + hi ns t rdgl rd high to dmag x low 11.0 +12 dt + hi ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). notes 1 data delay/setup: user must meet t dad or to t drld or synchronous specification t ssdati . 2 the falling edge of ms x, sw , bms , are referenced. 3 ack is not sampled on external memory accesses that use the internal wait state mode. for the first clkin cycle of a new external memory access, ack must be valid by t daak or t dsak or synchronous specification t sackc for wait state modes external , either , or both ( both , if the internal wait state is zero). for the second and subsequent cycles of a wait stated external memory access, synchronous specifications t sackc and t hackc must be met for wait state modes external , either , or both ( both , after internal wait states have completed). wr ack data rd address msx , sw bms t darl t rw t daak t rwr t drha t dsak dmag t hdrh t rdgl t drld t dad t hda figure 11. memory read?us master
rev. c adsp-21065l ?7 memory write?us master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21065l is the bus master when accessing external memory space. these switching characteristics also apply for bus master synchronous read/write timing (see synchronous read/write?us master below). if these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). an exception to this is the ack pin timing requirements as described in the note below. parameter min max unit timing requirements: t daak ack delay from address 1, 2 24.0 + 30 dt + w ns t dsak ack delay from wr low 1 19.5 + 24 dt + w ns switching characteristics: t dawh address, selects to wr deasserted 2 29.0 + 31 dt + w ns t dawl address, selects to wr low 2 3.5 + 6 dt ns t ww wr pulsewidth 24.5 + 25 dt + w ns t ddwh data setup before wr high 15.5 + 19 dt + w ns t dwha address hold after wr deasserted 0.0 + 1 dt + h ns t datrwh data disable after wr deasserted 3 1.0 + 1 dt + h 4.0 + 1 dt + h ns t wwr wr high to wr , rd low 4.5 + 7 dt + h ns t wrdgl wr high to dmag x low 11.0 + 13 dt + h ns t ddwr data disable before wr or rd low 3.5 + 6 dt + i ns t wde wr low to data enabled 4.5 + 6 dt ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). notes 1 ack is not sampled on external memory accesses that use the internal wait state mode. for the first clkin cycle of a new external memory access, ack must be valid by t daak or t dsak or synchronous specification t sackc for wait state modes external , either , or both ( both , if the internal wait state is zero). for the second and subsequent cycles of a wait stated external memory access, synchronous specifications t sackc and t hackc must be met for wait state modes external , either , or both ( both , after internal wait states have completed). 2 the falling edge of ms x, sw , and bms is referenced. 3 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. rd ack data wr address msx , sw bms t dawl t ww t daak t wwr t wde t ddwr t dwha t ddwh t dawh t dsak dmag t datrwh t wrdgl figure 12. memory write?us master
rev. c adsp-21065l ?8 synchronous read/write?us master use these specifications for interfacing to external memory systems that require clkin-relative timing or for accessing a slave adsp-21065l (in multiprocessor memory space). these synchronous switching characteristics are also valid during asynchronous memory reads and writes (see memory read?us master and memory write?us master). when accessing a slave adsp-21065l, these switching characteristics must meet the slave? timing requirements for synchronous read/writes (see synchronous read/write?us slave). the slave adsp-21065l must also meet these (bus master) timing require- ments for data and acknowledge setup and hold times. parameter min max unit timing requirements: t ssdati data setup before clkin 0.25 + 2 dt ns t hsdati data hold after clkin 4.0 ?2 dt ns t daak ack delay after address, ms x, sw , bms 1, 2 24.0 + 30 dt + w ns t sackc ack setup before clkin 1 2.75 + 4 dt ns t hack ack hold after clkin 2.0 ?4 dt ns switching characteristics: t dadro address, ms x, bms , sw delay after clkin 1 7.0 ?2 dt ns t hadro address, ms x, bms , sw hold after clkin 0.5 ?2 dt ns t drdo rd high delay after clkin 0.5 ?2 dt 6.0 ?2 dt ns t dwro wr high delay after clkin 0.0 ?3 dt 6.0 ?3 dt ns t drwl rd / wr low delay after clkin 7.5 + 4 dt 11.75 + 4 dt ns t ddato data delay after clkin 22.0 + 10 dt ns t dattr data disable after clkin 3 1.0 ?2 dt 7.0 ?2 dt ns t dbm bmstr delay after clkin 3.0 ns t hbm bmstr hold after clkin ?.0 ns w = (number of wait states specified in wait register) t ck . notes 1 data hold: user must meet t hda or t hdrh or synchronous specification t hdati . see system hold time calculation under test conditions for the calculation of hold times given capacitive and dc loads. 2 ack is not sampled on external memory accesses that use the internal wait state mode. for the first clkin cycle of a new external memory access, ack must be valid by t daak or t dsak or synchronous specification t sackc for wait state modes external , either , or both ( both , if the internal wait state is zero). for the second and subsequent cycles of a wait stated external memory access, synchronous specifications t sackc and t hackc must be met for wait state modes external , either , or both ( both , after internal wait states have completed). 3 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads.
rev. c adsp-21065l ?9 clkin address sw ack (in) rd data (out) wr t hadro t daak t drwl t sackc t hackc t hsdati t ssdati t drdo t dwro t dattr t ddato t drwl data (in) t dadro write cycle read cycle figure 13. synchronous read/write?us master
rev. c adsp-21065l ?0 synchronous read/write?us slave use these specifications for adsp-21065l bus master accesses of a slave? iop registers or internal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements. parameter min max unit timing requirements: t sadri address, sw setup before clkin 24.5 + 25 dt ns t hadri address, sw hold before clkin 4.0 + 8 dt ns t srwli rd / wr low setup before clkin 1 21.0 + 21 dt ns t hrwli rd / wr low hold after clkin ?.50 ?5 dt 7.5 + 7 dt ns t rwhpi rd / wr pulse high 2.5 ns t sdatwh data setup before wr h igh 4.5 ns t hdatwh data hold after wr h igh 0.0 ns switching characteristics: t sddato data delay after clkin 31.75 + 21 dt ns t dattr data disable after clkin 2 1.0 ?2 dt 7.0 ?2 dt ns t dack ack delay after clkin 29.5 + 20 dt ns t acktr ack disable after clkin 2 1.0 ?2 dt 6.0 ?2 dt ns notes 1 t srwli is sp ecified when multiprocessor mem ory sp ace wait state (mmsws bit in wait register) is disabled; when mmsws is ena bled, t srwli (min) = 17.5 + 18 dt. 2 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. for two adsp-21065ls to communicate synchronously as master and slave, certain master and slave specification combinations must be satisfied. do not compare specification values directly to calculate master/slave clock skew margins for those specific ations listed below. the following table shows the appropriate clock skew margin. table iv. bus master to slave skew margins master specification slave specification skew margin t ssdati t sddato t ck = 33.3 ns + 2.25 ns t ck = 30.0 ns + 1.50 ns t sackc t dack t ck = 33.3 ns + 3.00 ns t ck = 30.0 ns + 2.25 ns t dadro t sadri t ck = 33.3 ns n/a t ck = 30.0 ns + 2.75 ns t drwl (max) t srwli t ck = 33.3 ns + 1.50 ns t ck = 30.0 ns + 1.25 ns t drdo (max) t hrwli (max) t ck = 33.3 ns n/a t ck = 30.0 ns 3.00 ns t dwro (max) t hrwli (max) t ck = 33.3 ns n/a t ck = 30.0 ns 3.75 ns
rev. c adsp-21065l ?1 clkin address sw ack rd data (out) wr write access t sadri t hadri t dack t acktr t rwhpi t hrwli t srwli t sddato t dattr t srwli t hrwli t rwhpi t hdatwh t sdatwh data (in) read access figure 14. synchronous read/write?us slave
rev. c adsp-21065l ?2 multiprocessor bus request and host bus request use these specifications for passing of bus mastership between multiprocessing adsp-21065ls ( br x) or a host processor ( hbr , hbg ). parameter min max unit timing requirements: t hbgrcsv hbg low to rd / wr / cs valid 1 20.0 + 36 dt ns t shbri hbr setup before clkin 2 12.0 + 12 dt ns t hhbri hbr hold before clkin 2 6.0 + 12 dt ns t shbgi hbg setup before clkin 6.0 + 8 dt ns t hhbgi hbg hold before clkin high 1.0 + 8 dt ns t sbri br x, cpa setup before clkin 3 7.0 + 8 dt ns t hbri br x, cpa hold before clkin high 1.0 + 8 dt ns switching characteristics: t dhbgo hbg delay after clkin 8.0 ?2 dt ns t hhbgo hbg hold after clkin 1.0 ?2 dt ns t dbro br x delay after clkin 7.0 ?2 dt ns t hbro br x hold after clkin 1.0 ?2 dt ns t dcpao cpa low delay after clkin 11.5 ?2 dt ns t trcpa cpa disable after clkin 1.0 ?2 dt 5.5 ?2 dt ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 4 13.0 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 4 44.0 + 43 dt ns t ardytr redy (a/d) disable from cs or hbr h igh 4 10.0 ns notes 1 for first asynchronous access after hbr and cs asserted, addr 23-0 must be a nonmms value 1/2 t ck before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the host processor control of the adsp-21065l section of the adsp-21065l sharc user? manual , second edition. 2 only required for recognition in the current cycle. 3 cpa assertion must meet the setup to clkin; deassertion does not need to meet the setup to clkin. 4 (o/d) = open drain, (a/d) = active drive.
rev. c adsp-21065l ?3 clkin hbr hbg (out) brx (out) hbg (in) brx (in) hbr redy (o/d) cs hbg (out) t drdycs t hbgrcsv t trdyhg redy (a/d) t ardytr rd wr cs t shbri t hhbri t hhbgo t dhbgo t hbro t dbro t dcpao t trcpa t shbgi t sbri cpa (out) (o/d) cpa (in) (o/d) t hhbgi t hbri o/d = open drain, a/d = active drive figure 15. multiprocessor bus request and host bus request
rev. c adsp-21065l ?4 asynchronous read/write?ost to adsp-21065l use these specifications for asynchronous host processor accesses of an adsp-21065l, after the host has asserted cs and hbr (low). after the adsp-21065l returns hbg , the host can drive the rd and wr pins to access the adsp-21065l? iop registers. hbr and hbg are assumed low for this timing. writes can occur at a minimum interval of (1/2) t ck . parameter min max unit read cycle timing requirements: t sadrdl address setup / cs low before rd low * 0.0 ns t hadrdh address hold/ cs hold low after rd h igh 0.0 ns t wrwh rd / wr high width 6.0 ns t drdhrdy rd high delay after redy (o/d) disable 0.0 ns t drdhrdy rd high delay after redy (a/d) disable 0.0 ns switching characteristics: t sdatrdy data valid before redy disable from low 1.5 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 13.5 ns t rdyprd redy (o/d) or (a/d) low pulsewidth for read 28.0 + dt ns t hdarwh data disable after rd h igh 2.0 10.0 ns write cycle timing requirements: t scswrl cs low setup before wr low 0.0 ns t hcswrh cs low hold after wr h igh 0.0 ns t sadwrh address setup before wr h igh 5.0 ns t hadwrh address hold after wr h igh 2.0 ns t wwrl wr low width 7.0 ns t wrwh rd / wr high width 6.0 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0.0 ns t sdatwh data setup before wr h igh 5.0 ns t hdatwh data hold after wr h igh 1.0 ns switching characteristics: t drdywrl redy (o/d) or (a/d) low delay after wr / cs low 13.5 ns t rdypwr redy (o/d) or (a/d) low pulsewidth for write 7.75 ns note * not required if rd and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr23-0 must be a nonmms value 1/2 t clk before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see host inter- face, in the adsp-21065l sharc user? manual , second edition.
rev. c adsp-21065l ?5 t sadrdl redy (o/d) rd t drdyrdl t wrwh t hadrdh t hdarwh t rdyprd t drdhrdy t sdatrdy read cycle address/ cs data (out) redy (a/d) o/d = open drain, a/d = active drive t sdatwh t hdatwh t wwrl redy (o/d) wr t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy write cycle t sadwrh data (in) address redy (a/d) t scswrl cs t hcswrh figure 16. asynchronous read/write?ost to adsp-21065l
rev. c adsp-21065l ?6 three-state timing?us master, bus slave, hbr , sbts these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin a nd the sbts pin. t his timing is applicable to bus master transition cycles (btc) and host transition cycles (htc) as well as the sbts pin. parameter min max unit timing requirements: t stsck sbts setup before clkin 7.0 + 8 dt ns t htsck sbts hold before clkin 1.0 + 8 dt ns switching characteristics: t miena address/select enable after clkin 1.0 ?2 dt ns t miens strobes enable after clkin 1 ?.5 ?2 dt ns t mienhg hbg enable after clkin 2.0 ?2 dt ns t mitra address/select disable after clkin 3.0 ?4 dt ns t mitrs strobes disable after clkin 1 4.0 ?4 dt ns t mitrhg hbg disable after clkin 5.5 ?4 dt ns t daten data enable after clkin 2 10.0 + 5 dt ns t dattr data disable after clkin 2 1.0 ?2 dt 7.0 ?2 dt ns t acken ack enable after clkin 2 7.5 + 4 dt ns t acktr ack disable after clkin 2 1.0 ?2 dt 6.0 ?2 dt ns t mtrhbg memory interface disable before hbg low 3 2.0 + 2 dt ns t menhbg memory interface enable after hbg h igh 3 15.75 + dt ns notes 1 strobes = rd , wr , sw , dmag . 2 in addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 3 memory interface = address, rd , wr , ms x, sw , dmag x, bms (in eprom boot mode).
rev. c adsp-21065l ?7 clkin sbts ack memory interface t menhbg t mtrhbg hbg memory interface = address, rd , wr , ms x, sw , dmag x. bms (in eprom boot mode) t mitra, t mitrs, t mitrhg t stsck t htsck t dattr t daten t acktr t acken data memory interface t miena, t miens, t mienhg figure 17. three-state timing
rev. c adsp-21065l ?8 dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate transfers. for hand- shake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr 23-0 , rd , wr , sw , ms 3-0 , ack, and dmag signals. external mode cannot be used for transfers with sdram. for paced master mode, the data transfer is controlled by addr 23-0 , rd , wr , ms 3-0 , and ack (not dmag ). for paced master mode, the memory read-bus master, memory write-bus master, and synchronous read/write-bus master timing specifications for addr 23-0 , rd , wr , ms 3-0 , sw , data 31-0 , and ack also apply. parameter min max unit timing requirements: t sdrlc dmar x low setup before clkin 1 5.0 ns t sdrhc dmar x high setup before clkin 1 5.0 ns t wdr dmar x width low (nonsynchronous) 6.0 ns t sdatdgl data setup after dmag x low 2 15.0 + 20 dt ns t hdatidg data hold after dmag x high 0.0 ns t datdrh data valid after dmar x high 2 25.0 + 14 dt ns t dmarll dmar x low edge to low edge 18.0 + 14 dt ns t dmarh dmar x width high 6.0 ns switching characteristics: t ddgl dmag x low delay after clkin 14.0 + 10 dt 20.0 + 10 dt ns t wdgh dmag x high width 10.0 + 12 dt + hi ns t wdgl dmag x low width 16.0 + 20 dt ns t hdgc dmag x high delay after clkin 0.0 ?2 dt 6.0 ?2 dt ns t dadgh address select valid to dmag x high 28.0 + 16 dt ns t ddgha address select hold after dmag x high ?.0 ns t vdatdgh data valid before dmag x high 3 16.0 + 20 dt ns t datrdgh data disable after dmag x high 4 0.0 4.0 ns t dgwrl wr low before dmag x low 5.0 + 6 dt 8.0 + 6 dt ns t dgwrh dmag x low before wr high 18.0 + 19 dt + w ns t dgwrr wr high before dmag x high 0.75 + 1 dt 3.0 + 1 dt ns t dgrdl rd low before dmag x low 5.0 8.0 ns t drdgh rd low before dmag x high 24.0 + 26 dt + w ns t dgrdr rd high before dmag x high 0.0 2.0 ns t dgwr dmag x high to wr , rd low 5.0 + 6 dt + hi ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). notes 1 only required for recognition in the current cycle. 2 t sdatdgl is the data setup requirement if dmar x is not being used to hold off completion of a write. otherwise, if dmar x low holds off completion of the write, the data can be driven t datdrh after dmar x is brought high. 3 t vdatdgh is valid if dmar x is not being used to hold off completion of a read. if dmar x is used to prolong the read, then t vdatdgh = 8 + 9 dt + (n t ck ) where n equals the number of extra cycles that the access is prolonged. 4 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads.
rev. c adsp-21065l ?9 clkin t sdrlc dmar x data (from adsp-2106x to external device) data (from external device to adsp-2106x) rd (external memory to external device) wr (external device to external memory) t wdr t sdrhc t dmarh t dmarll t hdgc t wdgh t ddgl t wdgl dmag x t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t sdatdgl * ?emory read ?bus master,??emory write ?bus master,?and ?ynchronous read/write ?bus master timing specifications for addr 23? , rd , wr , sw , ms 3? , and ack also apply here. transfers between adsp-2106x internal memory and external device transfers between external device and external memory (external handshake mode) t ddgha address sw , ms x t dadgh * figure 18. dma handshake timing
rev. c adsp-21065l ?0 sdram interface?us master use these specifications for adsp-21065l bus master accesses of sdram. parameter min max unit timing requirements: t sdsdk data setup before sdclk 2.0 ns t hdsdk data hold after sdclk 1.25 ns switching characteristics: t dsdk1 first sdclk rise delay after clkin 9.0 + 6 dt 12.75 + 6 dt ns t dsdk2 second sdclk rise delay after clkin 25.5 + 22 dt 29.25 + 22 dt ns t sdk sdclk period 16.67 t ck /2 ns t sdkh sdclk width high 7.5 + 8 dt ns t sdkl sdclk width low 6.5 + 8 dt ns t dcadsdk command, address, data, delay after sdclk 1 10.0 + 5 dt ns t hcadsdk command, address, data, hold after sdclk 1 4.5 + 5 dt ns t sdtrsdk data three-state after sdclk 9.5 + 5 dt ns t sdensdk data enable after sdclk 2 6.0 + 5 dt ns t sdctr sdclk, command three-state after clkin 1 5.0 + 3 dt 9.75 + 3 dt ns t sdcen sdclk, command enable after clkin 1 5.0 + 2 dt 10.0 + 2 dt ns t sdatr address three-state after clkin ?.0 ?4 dt 3.0 ?4 dt ns t sdaen address enable after clkin 1.0 ?2 dt 7.0 ?2 dt ns notes 1 command = sdcke, ms x, ras , cas , sdwe , dqm, and sda10. 2 sdram controller adds one sdram clk three-stated cycle delay (t ck /2) on a read followed by a write. sdram interface?us slave these timing requirements allow a bus slave to sample the bus master? sdram command and detect when a refresh occurs. parameter min max unit timing requirements: t ssdkc1 first sdclk rise after clkin 6.50 + 16 dt 17.5 + 16 dt ns t ssdkc2 second sdclk rise after clkin 23.25 34.25 ns t scsdk command setup before sdclk * 0.0 ns t hcsdk command hold after sdclk * 2.0 ns note * command = sdcke, ras , cas , and sdwe .
rev. c adsp-21065l ?1 t hcsdk t scsdk t ssdkc1 t ssdkc2 t sdaen t sdatr t sdctr t hcadsdk t hcadsdk t sdtrsdk t dcadsdk t sdcen t sdsdk t dcadsdk t sdensdk t hdsdk t sdkl t sdkh t sdk t dsdk1 t dsdk2 clkin sdclk data (in) data (out) cmnd 1 addr (out) cmnd 1 (out) addr (out) sdclk (in) cmnd 2 (in) clkin notes 1 command = sdcke, ms x , ras , cas , sdwe , dqm , and sda10. 2 sdram controller adds one sdram clk three-stated cycle delay ( t ck /2) on a read followed by a write. figure 19. sdram interface
rev. c adsp-21065l ?2 serial ports parameter min max unit external clock timing requirements: t sfse tfs/rfs setup before tclk/rclk 1 4.0 ns t hfse tfs/rfs hold after tclk/rclk 1 4.0 ns t sdre receive data setup before rclk 1 1.5 ns t hdre receive data hold after rclk 1 4.0 ns t sclkw tclk/rclk width 9.0 ns t sclk tclk/rclk period t ck ns internal clock timing requirements: t sfsi tfs setup before tclk 2 ; rfs setup before rclk 1 8.0 ns t hfsi tfs/rfs hold after tclk/rclk 1 1.0 ns t sdri receive data setup before rclk 1 3.0 ns t hdri receive data hold after rclk 1 3.0 ns external or internal clock switching characteristics: t dfse rfs delay after rclk (internally generated rfs) 2 13.0 ns t hofse rfs hold after rclk (internally generated rfs) 2 3.0 ns external clock switching characteristics: t dfse tfs delay after tclk (internally generated tfs) 2 13.0 ns t hofse tfs hold after tclk (internally generated tfs) 2 3.0 ns t ddte transmit data delay after tclk 2 12.5 ns t hdte transmit data hold after tclk 2 4.0 ns internal clock switching characteristics: t dfsi tfs delay after tclk (internally generated tfs) 2 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 2 ?.5 ns t ddti transmit data delay after tclk 2 7.5 ns t hdti transmit data hold after tclk 2 0.0 ns t sclkiw tclk/rclk width (t sclk /2) ?2.5 (t sclk /2) + 2.5 ns enable and three-state switching characteristics: t dtene data enable from external tclk 2 5.0 ns t ddtte data disable from external rclk 2 10.0 ns t dteni data enable from internal tclk 2 0.0 ns t ddtti data disable from internal tclk 2 3.0 ns t dclk tclk/rclk delay from clkin 18.0 + 6 dt ns t dptr sport disable after clkin 14.0 ns external late frame sync t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 3, 4 10.5 ns t dtenlfse data enable from late fs or mce = 1, mfd = 0 3, 4 3.5 ns t ddtlsck data delay from tclk/rclk for late external tfs or external rfs with mce = 1, mfd = 0 3, 4 12.0 ns t dtenlsck data enable from rclk/tclk for late external fs or mce = 1, mfd = 0 3, 4 4.5 ns notes to determine whether communication is possible between two devices at clock speed n, the following specifications must be confi rmed: 1) frame sync delay and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) sclk width. 1 referenced to sample edge. 2 referenced to drive edge. 3 mce = 1, tfs enable and tfs valid follow t ddtenfs and t ddtlfse. 4 if external rfs/tfs setup to rclk/tclk > t sclk /2 then t ddtlsck and t dtenlsck apply; otherwise t ddtlfse and t dtenlfs apply. * word selected timing for i 2 s mode is the same as tfs/rfs timing (normal framing only).
rev. c adsp-21065l ?3 dt dt t ddtte t ddten t ddtti t ddtin drive edge drive edge drive edge drive edge tclk / rclk tclk / rclk tclk (ext) tfs ("late", ext.) t sdri rclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive?internal clock t sdre data receive?external clock rclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkw t hofse note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddti t hdti tclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hofsi data transmit?internal clock t ddte t hdte tclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkw t hofse data transmit?external clock clkin sport enable and three-state latency is two cycles t dptr sport disable delay from instruction t dclk low to high only tclk (int) rclk (int) tclk, rclk tfs, rfs, dt note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. tclk (int) tfs ("late", int.) figure 20. serial ports
rev. c adsp-21065l ?4 t sfse/i drive sample drive t dtenlfse t ddtlfse external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs late external tfs t hofse/i t hdte/i t ddte/i t sfse/i drive sample drive t dtenlfse t ddtlfse 1st bit 2nd bit dt tclk tfs t hofse/i t hdte/i t ddte/i figure 21. external late frame sync (frame sync setup < t sclk /2) drive sample drive t dtenlsck external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs late external tfs t hofse / i t hdte / i t ddte / i t ddtlsck t sfse / i drive sample drive t dtenlsck 1st bit 2nd bit dt tclk tfs t hofse / i t hdte / i t ddte / i t ddtlsck t sfse / i figure 22. external late frame sync (frame sync setup > t sclk /2)
rev. c adsp-21065l ?5 jtag test access port and emulation parameter min max unit timing requirements: t tck tck period t ck ns t stap tdi, tms setup before tck high 3.0 ns t htap tdi, tms hold after tck high 3.0 ns t ssys system inputs setup before tck low 1 7.0 ns t hsys system inputs hold after tck low 1 12.0 ns t trstw trst pulsewidth 4 t ck ns switching characteristics: t dtdo tdo delay from tck low 11.0 ns t dsys system outputs delay after tck low 2 15.0 ns notes 1 system inputs = data 31-0 , addr 23-0 , rd , wr , ack, sbts , sw , hbr , hbg , cs , dmar 1 , dmar 2 , br 2-1 , id 1-0 , irq 2-0 , flag 11-0 , dr0x, dr1x, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bsel, bms , clkin, reset , sdclk 0 , ras , cas , sdwe , sdcke, pwm_eventx. 2 system outputs = data 31-0 , addr 23-0 , ms 3-0 , rd , wr , ack, sw , hbg , redy, dmag1 , dmag2, br 2-1 , cpa , flag 11-0 , pwm_eventx, dt0x, dt1x, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, bms , sdclk0, sdclk1, dqm, sda10, ras , cas , sdwe , sdcke, bm, xtal. tck t stap t tck t htap t dtdo t ssys t hsys t dsys tms tdi tdo system inputs system outputs figure 23. jtag test access port and emulation
rev. c adsp-21065l ?6 output drive current source voltage ? v 80 0 3.50 source current ? ma 0.50 1.00 1.50 2.00 2.50 3.00 60 ?40 ?100 ?120 20 ?20 40 0 ?80 ?60 3.3v, +25 c 3.6v, ?40 c 3.1v, +100 c 3.6v, ?40 c v ol v oh 3.1v, +85 c 3.1v, +100 c 3.1v, +85 c 3.3v, +25 c figure 24. typical drive currents test conditions output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by d v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation: t cv i decay l l = d the output disable time t dis is the difference between t measured and t decay as shown in figure 26. the time t measured is the interval from when the reference signal switches to when the output voltage decays d v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with d v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose d v to be the difference between the adsp-21065l? output voltage and the input threshold for the device requiring the hold time. a typical d v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). reference signal t dis output starts driving v oh (measured) ? v v ol (measured) + v t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t ena t decay output figure 25. output enable +1.5v 50pf to output pin i ol i oh figure 26. equivalent device loading for ac measure- ments (includes all fixtures) input or output 1.5v 1.5v figure 27. voltage reference levels for ac measure- ments (except output enable/disable)
rev. c adsp-21065l ?7 capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins. the delay and hold specifications given should be derated by a factor of l.8 ns/50 pf for loads other than the nominal value of 50 pf. figure 28 and figure 29 show how output rise time varies with capacitance. figure 30 shows graphically how output delays and hold vary with load capaci- tance. (note that this graph or derating does not apply to output disable delays; see the previous section output disable time under test conditions.) the graphs of figure 28, figure 29, and figure 30 may not be linear outside the ranges shown. load capacitance ? pf 0 0 200 20 rise and fall times ? ns 40 60 80 100 120 140 160 180 2 rise time fall time 4 6 8 10 12 14 16 18 figure 28. typical rise and fall time (10%?0% v dd ) load capacitance ? pf 8.0 4.0 0 0200 20 rise and fall times ? ns 40 60 80 100 120 140 160 180 7.0 6.0 2.0 1.0 5.0 3.0 rise time fall time figure 29. typical rise and fall time (0.8 v?.0 v) load capacitance ? pf output delay or hold ? ns 5 ?2 0 140 20 40 60 80 100 120 4 3 2 1 0 ?1 160 180 200 6 figure 30. typical output delay or hold
rev. c adsp-21065l ?8 power dissipation total power dissipation has two components: one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation depends on the sequence in which instructions execute and the data operands involved. see i ddin calculation in electrical characteristics section. internal power dissipation is calculated this way: p int = i ddin v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins that switch during each cycle (o) the maximum frequency at which the pins can switch (f) the load capacitance of the pins (c) the voltage swing of the pins (v dd ). the external component is calculated using: p ext = o c v dd 2 f the load capacitance should include the processor? package capacitance (c in ). the frequency f includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/t ck while in sdram burst mode. example: estimate p ext with the following assumptions: ? system with one bank of external memory (32-bit) ?wo 1m 16 sdram chips, each with a control signal load of 3 pf and a data signal load of 4 pf external data writes occur in burst mode, two every 1/t ck cycles, a potential frequency of 1/t ck cycles/s. assume 50% pin switching the external sdram clock rate is 60 mhz (2/t ck ). the p ext equation is calculated for each class of pins that can drive: table v. external power calculations pin # of % type pins switching c f v dd 2 = p ext address 11 50 10.7 30 mhz 10.9 v = 0.019 w ms 0 10 10.7 10.9 v = 0.000 w sdwe 10 10.7 10.9 v = 0.000 w data 32 50 7.7 30 mhz 10.9 v = 0.042 w sdram clk 1 10.7 30 mhz 10.9 v = 0.007 w p ext = 0.068 w a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation. (i ddin see calculation in electrical characteristics section): p total = p ext + ( i ddin v dd ) note that the conditions causing a worst-case p ext differ from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). note also that it is not common for an appli- cation to have 100% or even 50% of the outputs switching simultaneously. environmental conditions thermal characteristics the adsp-21065l is offered in a 208-lead mqfp and a 196- ball mini-bga package. the adsp-21065l is specified for a case temperature (t case ) . to ensure that t case is not exceeded, an air flow source may be used. t case = t amb + ( pd q ca ) t case =c ase temperature (measured on top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation) q j c = 7.1 c/w for 208-lead mqfp q j c = 5.1 c/w for 196-ball mini-bga airflow table vi. thermal characteristics (208-lead mqfp) (linear ft./min.) 0 100 200 400 600 q ca ( c/w) 24 20 19 17 13 table vii. 196-ball mini-bga (linear ft./min.) 0 200 400 q ca ( c/w) 38 29 23
rev. c adsp-21065l ?9 pin pin pin pin pin pin pin pin pin pin no. name no. name no. name no. name no. name 1 vdd 43 cas 85 vdd 127 data28 169 addr17 2 rfs0 44 sdwe 86 data3 128 data29 170 addr16 3 gnd 45 vdd 87 data4 129 gnd 171 addr15 4 rclk0 46 dqm 88 data5 130 vdd 172 vdd 5 dr0a 47 sdcke 89 gnd 131 vdd 173 addr14 6 dr0b 48 sda10 90 data6 132 data30 174 addr13 7 tfs0 49 gnd 91 data7 133 data31 175 addr12 8 tclk0 50 dmag 19 2 data8 134 flag7 176 vdd 9 vdd 51 dmag 293 vdd 135 gnd 177 gnd 10 gnd 52 hbg 94 gnd 136 flag6 178 addr11 11 dt0a 53 bmstr 95 vdd 137 flag5 179 addr10 12 dt0b 54 vdd 96 data9 138 flag4 180 addr9 13 rfs1 55 cs 97 data10 139 gnd 181 gnd 14 gnd 56 sbts 98 data11 140 vdd 182 vdd 15 rclk1 57 gnd 99 gnd 141 vdd 183 addr8 16 dr1a 58 wr 100 data12 142 nc 184 addr7 17 dr1b 59 rd 101 data13 143 id1 185 addr6 18 tfs1 60 gnd 102 nc 144 id0 186 gnd 19 tclk1 61 vdd 103 nc 145 emu 187 gnd 20 vdd 62 gnd 104 data14 146 tdo 188 addr5 21 vdd 63 redy 105 vdd 147 trst 189 addr4 22 dt1a 64 sw 106 gnd 148 tdi 190 addr3 23 dt1b 65 cpa 107 data15 149 tms 191 vdd 24 pwm_event1 66 vdd 108 data16 150 gnd 192 vdd 25 gnd 67 vdd 109 data17 151 tck 193 addr2 26 pwm_event0 68 gnd 110 vdd 152 bsel 194 addr1 27 br1 69 ack 111 data18 153 bms 195 addr0 28 br2 70 ms 0 112 data19 154 gnd 196 gnd 29 vdd 71 ms 1 113 data20 155 gnd 197 flag0 30 clkin 72 gnd 114 gnd 156 vdd 198 flag1 31 xtal 73 gnd 115 nc 157 reset 199 flag2 32 vdd 74 ms 2 116 data21 158 vdd 200 vdd 33 gnd 75 ms 3 117 data22 159 gnd 201 flag3 34 sdclk1 76 flag11 118 data23 160 addr23 202 nc 35 gnd 77 vdd 119 gnd 161 addr22 203 nc 36 vdd 78 flag10 120 vdd 162 addr21 204 gnd 37 sdclk0 79 flag9 121 data24 163 vdd 205 irq 0 38 dmar 18 0 flag8 122 data25 164 addr20 206 irq 1 39 dmar 28 1 gnd 123 data26 165 addr19 207 irq 2 40 hbr 82 data0 124 vdd 166 addr18 208 nc 41 gnd 83 data1 125 gnd 167 gnd 42 ras 84 data2 126 data27 168 gnd 208-lead mqfp pin configuration
rev. c adsp-21065l ?0 208-lead mqfp pin 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 189 188 187 186 185 184 183 182 181 180 190 179 178 177 175 174 173 172 171 170 176 169 168 167 165 164 163 162 161 160 159 158 157 166 71 72 73 74 75 76 77 78 79 80 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 81 82 83 84 86 87 88 89 90 85 91 92 93 94 96 97 98 99 95 100 101 102 103 104 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 41 43 42 45 44 50 49 48 47 46 52 51 152 153 154 155 150 151 156 148 149 143 144 14 5 146 141 142 140 147 138 139 134 135 13 6 137 132 133 130 131 128 129 125 126 12 7 123 124 121 122 120 117 118 119 116 114 115 112 113 107 108 10 9 110 111 105 106 oo bmstr pin 1 identifier vdd cs sbts gnd wr rd gnd vdd gnd redy sw cpa vdd vdd gnd ack ms 0 ms 1 gnd gnd ms 2 ms 3 flag11 vdd flag10 flag9 flag8 gnd data0 data1 data2 vdd data3 data4 data5 gnd data6 data7 data8 vdd gnd vdd data9 data10 data11 gnd data12 data13 nc nc data14 nc irq 2 irq 1 irq 0 gnd nc nc flag3 vdd vdd rsf0 gnd rclk0 dr0a dr0b tfs0 tclk0 vdd gnd dt0a dt0b rfs1 gnd rclk1 dr1a dr1b tfs1 tclk1 vdd vdd dt1a dt1b pwm event1 gnd pwm event0 br1 br2 vdd clkin xtal vdd gnd sdclk1 gnd vdd sdclk0 dmar 1 dmar 2 hbr gnd ras sdwe vdd dqm sdcke sda10 gnd dmag 1 dmag 2 hbg gnd gnd bms bsel tck gnd tms tdi trst tdo emu id0 id1 nc vdd vdd gnd gnd vdd vdd gnd gnd vdd vdd gnd gnd vdd data15 gnd vdd vdd flag2 flag1 flag0 gnd addr0 addr1 addr2 vdd vdd addr3 addr4 addr5 gnd gnd addr6 addr7 addr8 vdd gnd addr9 addr10 addr11 gnd vdd addr12 addr13 addr14 vdd addr15 addr16 addr17 gnd gnd addr18 addr19 addr20 vdd addr21 addr22 addr23 gnd vdd reset cas data16 data17 data18 data19 data20 data22 data21 nc data23 data24 data25 data26 data27 data28 data29 data30 data31 flag7 flag6 flag5 flag4 nc = no connect top view (not to scale) adsp-21065l
rev. c adsp-21065l ?1 outline dimensions 208-lead metric quad flat package [mqfp] (s-208-2) dimensions shown in millimeters 0.20 0.09 3.60 3.40 3.20 0.50 0.25 0.08 max (lead coplanarity) view a rotated 90 ccw 1 208 157 156 105 104 53 52 top view (pins down) 0.50 bsc 28.20 28.00 sq 27.80 0.27 0.17 (lead pitch) (lead width) seating plane 4.10 max 0.75 0.60 0.45 notes: 1. the actual position of each lead is within 0.08 from its ideal position when measured in the lateral direction. 2. center dimensions are nominal. 3. dimensions are in millimeters and comply with jedec standard ms-029, fa-1. 30.85 30.60 sq 30.35 view a pin 1 indicator
rev. c adsp-21065l ?2 196-ball mini-bga pin configuration ball # name ball # name ball # name ball # name ball # name a1 nc1 b1 dr0a c1 tclk0 d1 rclk1 e1 tfs1 a2 nc2 b2 rfs0 c2 rclk0 d2 tfs0 e2 dt0b a3 flag2 b3 irq0 c3 irq2 d3 dr0b e3 dt0a a4 addr0 b4 flag0 c4 flag3 d4 irq1 e4 rfs1 a5 addr3 b5 addr2 c5 addr1 d5 flag1 e5 vdd a6 addr6 b6 addr5 c6 addr4 d6 vdd e6 gnd a7 addr7 b7 addr9 c7 addr10 d7 vdd e7 gnd a8 addr8 b8 addr12 c8 addr13 d8 vdd e8 gnd a9 addr11 b9 addr15 c9 addr16 d9 vdd e9 gnd a10 addr14 b10 addr19 c10 addr20 d10 vdd e10 vdd a11 addr17 b11 addr21 c11 addr22 d11 bms e11 id0 a12 addr18 b12 addr23 c12 reset d12 tms e12 tdi a13 nc8 b13 gnd c13 bsel d13 trst e13 id1 a14 nc7 b14 tck c14 tdo d14 emu e14 flag4 f1 tclk1 g1 pwm_ h1 pwm_ j1 clkin k1 dmar1 event1 event0 f2 dr1b g2 dt1b h2 br1 j2 xtal k2 sdclk0 f3 dr1a g3 dt1a h3 br2 j3 sdclk1 k3 hbr f4 vdd g4 vdd h4 vdd j4 vdd k4 sdwe f5 gnd g5 gnd h5 gnd j5 gnd k5 vdd f6 gnd g6 gnd h6 gnd j6 gnd k6 gnd f7 gnd g7 gnd h7 gnd j7 gnd k7 gnd f8 gnd g8 gnd h8 gnd j8 gnd k8 gnd f9 gnd g9 gnd h9 gnd j9 gnd k9 gnd f10 gnd g10 gnd h10 gnd j10 gnd k10 vdd f11 vdd g11 vdd h11 vdd j11 vdd k11 data19 f12 flag6 g12 data31 h12 data28 j12 data24 k12 data21 f13 flag5 g13 data30 h13 data27 j13 data25 k13 data20 f14 flag7 g14 data29 h14 data26 j14 data23 k14 data22 l1 dmar2 m1 ras n1 dqm p1 nc3 l2 cas m2 sdcke n2 hbg p2 nc4 l3 sda10 m3 dmag1 n3 bmstr p3 gnd l4 dmag2 m4 cs n4 sbts p4 wr l5 vdd m5 rd n5 redy p5 sw l6 vdd m6 cpa n6 gnd p6 ms0 l7 vdd m7 ack n7 ms1 p7 ms2 l8 vdd m8 flag10 n8 flag11 p8 ms3 l9 vdd m9 data2 n9 data1 p9 flag9 l10 data8 m10 data5 n10 data4 p10 flag8 l11 data13 m11 data9 n11 data7 p11 data0 l12 data16 m12 data12 n12 data10 p12 data3 l13 data17 m13 data14 n13 data11 p13 data6 l14 data18 m14 data15 n14 nc6 p14 nc5
rev. c adsp-21065l ?3 196-ball mini-bga pin configuration 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p nc7 tck tdo emu flag4 flag7 data29 data26 data23 data22 data18 data15 nc6 nc5 nc8 gnd bsel trst id1 flag5 data30 data27 data25 data20 data17 data14 data11 data6 addr18 addr23 reset tms tdi flag6 data31 data28 data24 data21 data16 data12 data10 data3 addr17 addr21 addr22 bms id0 vdd vdd vdd vdd data19 data13 data9 data7 data0 addr14 addr19 addr20 vdd vdd gnd gnd gnd gnd vdd data8 data5 data4 flag8 addr11 addr15 addr16 vdd gnd gnd gnd gnd gnd gnd vdd data2 data1 flag9 addr8 addr12 addr13 vdd gnd gnd gnd gnd gnd gnd vdd flag10 flag11 ms3 addr7 addr9 addr10 vdd gnd gnd gnd gnd gnd gnd vdd ack ms1 ms2 addr6 addr5 addr4 vdd gnd gnd gnd gnd gnd gnd vdd cpa gnd ms0 addr3 addr2 addr1 flag1 vdd gnd gnd gnd gnd vdd vdd rd redy sw addr0 flag0 flag3 irq1 rfs1 vdd vdd vdd vdd sdwe dmag2 cs sbts wr flag2 irq0 irq2 dr0b dt0a dr1a dt1a br2 sdclk1 hbr sda10 dmag1 bmstr gnd nc2 rfs0 rclk0 tfs0 dt0b dr1b dt1b br1 xtal sdclk0 cas sdcke hbg nc4 nc1 dr0a tclk0 rclk1 tfs1 tclk1 pwm_ event1 pwm_ event0 clkin dmar1 dmar2 ras dqm nc3
rev. c adsp-21065l ?4 c00172??/03(c) printed in u.s.a. outline dimensions 196-lead chip scale ball grid array [cspbga] dimensions shown in millimeters detail b detail a seating plane detail a ball diameter 0.55 nom 0.20 max ball coplanarity 13.00 bsc a b c d e f g h j k l m n p 9 8 7 6 5 4 3 2 1 detail b 1.00 bsc 15.00 bsc sq top view bottom view 1.00 bsc 1.90 1.75 1.55 13.00 bsc 10 11 12 13 14 0.70 0.60 0.50 0.60 0.50 0.35 0.75 0.70 0.65 1.10 1.00 0.90 1.10 1.00 0.90 notes: 1. the actual position of the ball grid is within 0.30 of its ideal position relative to the package edges. 2. the actual position of each ball is within 0.10 of its ideal position relative to the ball grid. 3. dimensions comply with jedec standard ms-034aae-1. 4. center dimensions are nominal. ordering guide part case temperature instruction on-chip operating package number range rate sram voltage options adsp-21065lks-240 0 c to +85 c 60 mhz 544 kbit 3.3 v mqfp adsp-21065lcs-240 ?0 c to +100 c 60 mhz 544 kbit 3.3 v mqfp adsp-21065lkca-240 0 c to +85 c 60 mhz 544 kbit 3.3 v mini-bga adsp-21065lks-264 0 c to +85 c 66 mhz 544 kbit 3.3 v mqfp adsp-21065lkca-264 0 c to +85 c 66 mhz 544 kbit 3.3 v mini-bga ADSP-21065LCCA-240 ?0 c to +100 c 60 mhz 544 kbit 3.3 v mini-bga revision history location page 6/03?ata sheet changed from rev. b to rev. c. edit to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 removal of overbar from dqm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal edit to power dissipation adsp-21065l (equations above table iii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 addition to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 update to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 44

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